1. Field
Cache coherency in a point-to-point interconnected multi-processor system.
2. Background
Processors in a multi-processor (MP) system may be connected with a multi-drop bus or a point-to-point interconnection network. A point-to-point interconnection network may provide full connectivity in which every processor is directly connected to every other processor in the system. A point-to-point interconnection network may alternatively provide partial connectivity in which a processor reaches another processor by routing through one or more intermediate processors.
Each processor in a MP system typically has a local cache to store data and code most likely to be reused. To ensure cache coherency, processors need to be informed of any transactions that may alter the coherency states of the data items in their local caches. One approach to cache coherency is directory-based where a centralized directory keeps track of all memory transactions that may alter the coherency states of the cached items. A coherency state indicates whether a data item is modified by a processor (the “M” state), exclusively owned by a processor (the “E” state), shared by multiple processors (the “S” state), or invalidated (the “I” state). The implementation of a directory often incurs substantial hardware cost.
Another approach to cache coherency is based on message exchanges among processors. For example, processors may exchange snoop messages to notify other processors of memory transactions that may alter the coherency states of cached data items. In a bus-connected MP system when a processor fetches a data item from main memory, all of the other processors can snoop the common bus at the sane time. In a point-to-point interconnection network, a processor sends snoop messages to all the other processors when it conducts a memory transaction. Snoop messages can be sent directly from one processor to all the other processors in a fully-connected point-to-point interconnection network. However, to save hardware cost, a typical point-to-point interconnection network often provides partially connectivity which does not provide direct links between all processors.